Self-powered analog computing architecture with energy monitoring to enable machine-learning vision at the edge

ABSTRACT

An analog computing method includes the steps of: (a) generating a biasing current (IWi) using a constant gm bias circuit operating in the subthreshold region for ultra-low power consumption, wherein gm is generated by PMOS or NMOS transistors, the circuit including a switched capacitor resistor; and (b) multiplying the biasing current by an input voltage using a differential amplifier multiplication circuit to generate an analog voltage output (VOi). In one or more embodiments, the method is used in a vision application, where the biasing current represents a weight in a convolution filter and the input voltage represents a pixel voltage of an acquired image.

CROSS REFERENCE TO RELATED APPLICATION

This application claims priority from U.S. Provisional Patent Application No. 62/823,328 filed on Mar. 25, 2019 and entitled SELF-POWERED ANALOG COMPUTING ARCHITECTURE WITH ENERGY MONITORING TO ENABLE MACHINE-LEARNING VISION AT THE EDGE, which is hereby incorporated by reference.

BACKGROUND

The internet-of-things (IoT) is the way in which networking sensors are placed on everyday physical objects to perform meaningful sensing and communication. Since its conception, IoT has been touted as the next wave of computing with exponential growth prospects. However, the growth outlook of IoT has recently been tempered due to the technological challenges that still need to be overcome. IoT devices should be seamlessly deployed in our environment without the need for maintenance, such as through a battery-less device that runs on harvested energy. However, harvested energy is low and system power consumption is high. Further, there is a need to enable edge-computing to reduce the amount of data and associated traffic. Edge-computing incorporates processing abilities inside the edge-device, and provides a way for an efficient use of energy and spectrum [1-3]. Furthermore, IoT edge-devices have to address modern computing needs of machine-learning and deep-learning to have a dedicated computing infrastructure for even higher power gains [4, 5].

Power efficiency and effective use of available spectrum by IoT devices are two core issues around which IoT networks are being developed. A recent report from McKinsey Inc. identifies self-powered operation of IoT devices as the key challenge that needs to be overcome to realize the full potential and growth of IoT [6]. To that end, researchers have been developing ultra-low power (ULP) and energy harvesting circuit and system design techniques. A typical approach is to make more energy available for the system through efficient and ULP energy harvesting while also reducing the power consumption of existing circuits and system architecture to overcome the energy gap [7]. The latest ULP design techniques are leading to an overhaul of existing circuit and system architectures. The disclosure herein relates to self-powered IoT devices that can implement vision. Techniques disclosed herein relate to a new machine-learning, application specific integrated circuit (ASIC) that has a high precision and reconfigurable analog computing infrastructure to realize several orders of magnitude improvement in power efficiency. The disclosure also relates to an energy-monitoring system (EMS) to scale system operation based on available energy to achieve infinite lifetime.

Computer vision involves extracting meaningful information from images or videos. Its usage can be found in variety of real world applications such as automatic inspection, identification, control based on incoming videos or images (e.g., self-driving cars and robots), feature-extraction, and human-machine interactions among others. Ever since the overwhelming victory of deep convolutional neural-network (CNN) for image classification at the Imagenet challenge [8], CNN based deep-learning and machine learning algorithms have gained popularity in vision applications [9-18]. These CNN algorithms achieved much higher accuracy for image classification and evolved into more deeper and involved networks. However, the hardware resource requirement for running these algorithms is significantly high. Some of the hardware that can efficiently execute these networks are Intel's Haswell with a CPU architecture [19], Nvidia's Tesla-K80 with a GPU architecture [20], and Google's Tensor Processing Unit (TPU) which is a neural-network based ASIC [21]. The thermal design power (TDP) for Haswell is 145 W, for Nvidia's K-80 is 150 W, and 75 W for Google's TPU. The peak power is often 1.5× larger than the TDP [22], and above designs are power constrained from thermal point of view (POV) and not from lifetime POV. The energy constrained devices that reside at the edge of IoT needs to have power consumption at pW and nW level such as system-on-chips (SoC) [7, 23-26]. A gap of 8-9 orders of magnitude exists between the power consumption needed for running CNNs and power available at the edge. Device scaling is unlikely to reduce this power gap by a significant amount as CMOS scaling is expected to end by 2024 [27]. There is a need to develop dedicated hardware, such as ASICs where hardware and algorithms are developed in communion [28]. Embodiments disclosed herein relate to an analog computing infrastructure for vision applications operating in an energy constrained environment.

Analog Hardware for Machine-Learning

Analog computing has been known to be highly efficient in terms of both area and power for realizing a given function on the chip. Compared to digital computing, where transistors are operated at two extreme operating states (on and off), analog computing can make use of the entire range of the operating current and voltage of a transistor, incorporating a vast amount of information per transistor with high power efficiency. These features of analog computing have become highly appealing to the modern computing needs where higher area and/or higher energy efficiency is needed, such as for the implementation of machine learning, deep learning, computation at the edge for IoT applications. However, analog computing has traditionally suffered from issues such as reliability, programmability, long design time, power consumption, and high susceptibility to variations, which led to a swift rise of digital computing. The spread of digital computing was significantly aided by CMOS technology scaling, as more and more transistors can be added on the silicon to scale up the computational power per-unit area. However, CMOS scaling is expected to end by 2024 [27], and adding more compute capability by way of technology scaling is no longer as trivial as it used to be.

The classical advantages of analog computing have again started to appear in recently published works. Advantages of analog computing in implementing hardware to solve partial and ordinary differential equations (PDE and ODE) have been reported in recent publications [29-32]. A recent paper at MICRO uses an analog accelerator to implement a PDE solver, and achieved 5.7× performance improvement and over 11.6× reduction in power consumption [33]. Analog computing is considered particularly promising for implementing machine-learning algorithm as it can significantly reduce the amount of hardware needed for complex networks [34-38]. In [37], authors implemented a deep learning hardware using analog computing elements to achieve a significantly higher power and area efficiency when compared to a similar hardware implemented using digital hardware [36]. Memristor based analog computing designs that can implement image processing networks have also been reported recently [39, 40]. A simulation based analog computing implementation of first five stages of GoogleNet has also been reported to showcase power and area benefits of analog [41].

BRIEF SUMMARY OF THE DISCLOSURE

An analog computing method in accordance with one or more embodiments includes the steps of: (a) generating a biasing current (IWi) using a constant gm bias circuit operating in the subthreshold region for ultra-low power consumption, wherein gm is generated by PMOS or NMOS transistors, the circuit including a switched capacitor resistor; and (b) multiplying the biasing current by an input voltage using a differential amplifier multiplication circuit to generate an analog voltage output (VOi). In one or more embodiments, the method is used in a vision application, where the biasing current represents a weight in a convolution filter and the input voltage represents a pixel voltage of an acquired image.

An analog computing circuit in accordance with one or more embodiments is also disclosed herein. The analog computing circuit includes a constant gm bias circuit operating in the subthreshold region for ultra-low power consumption for generating a biasing current (IWi), wherein gm in the constant gm bias circuit is generated by PMOS or NMOS transistors. The constant gm bias circuit includes a switched capacitor resistor. The analog computing circuit also includes a differential amplifier multiplication circuit coupled to the constant gm bias circuit for receiving the biasing current and an input voltage and multiplying the biasing current by the input voltage to generate an analog voltage output (VOi).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A shows an exemplary BJT-based current source for constant gm biasing.

FIG. 1B shows an exemplary differential amplifier with an SCR and decoupling capacitors in accordance with one or more embodiments.

FIG. 1C shows differential amplifier gain variance with temperature.

FIG. 1D shows process variation of differential amplifier gain at 50° C.

FIG. 1E shows an exemplary sub-threshold gm-C filter with PTAT bias in accordance with one or more embodiments.

FIG. 1F shows an exemplary gm-C biquad filter in accordance with one or more embodiments.

FIG. 1G shows variation of cut off frequency of a biquad LPF with temperature.

FIG. 1H shows process variation of cut off frequency of a biquad filter.

FIG. 2 shows an exemplary CNN architecture used for CIFAR-10 classification.

FIG. 3A shows the circuit architecture of a 3-T pixel interfaced with an analog multiplier.

FIG. 3B shows a timing diagram for the circuit of FIG. 3A.

FIG. 4A shows the circuit architecture of an analog multiplier using a diff-amp biased in sub-threshold with a bias current in accordance with one or more embodiments.

FIG. 4B shows the simulation results of the analog multiplier circuit of FIG. 4A.

FIG. 5A shows an exemplary multiply and accumulate (MAC) unit in accordance with one or more embodiments.

FIGS. 5B and 5C illustrate the voltage output in the first phase and second phase of operation, respectively, of the MAC unit of FIG. 5A.

FIG. 6A illustrates an exemplary A-ReLU circuit in accordance with one or more embodiments.

FIG. 6B illustrates an exemplary max-pooling circuit in accordance with one or more embodiments.

FIG. 7 shows an exemplary voltage scaling circuit using capacitive charge sharing in accordance with one or more embodiments.

FIG. 8A shows the circuit architecture of an alternate analog multiplier using a diff-amp biased in sub-threshold with a bias current in accordance with one or more embodiments.

FIG. 8B shows the simulation results of the analog multiplier circuit of FIG. 8A.

FIG. 9A illustrates exemplary parallel analog multiplication circuits in accordance with one or more embodiments.

FIG. 9B illustrates an exemplary accumulation circuit in accordance with one or more embodiments.

FIG. 10 shows a conceptual architecture of a vision ASIC in accordance with one or more embodiments.

DETAILED DESCRIPTION

One or more embodiments disclosed herein relate to an analog processing vision ASIC with several orders of magnitude higher power efficiency. A more general and precise analog processing architecture that can be utilized for many deep learning networks will be developed. A highly stable, sub-threshold based analog computing platform can reduce the power consumption, thanks to sub-threshold operation, and reduce the variation in analog computation by three orders of magnitude, providing high precision circuit elements.

Precision Analog Circuit Elements

Disclosed herein are high precision analog circuit components that is used for analog computing elements machine-learning vision ASIC. The architecture operates device in sub-threshold region. Sub-threshold biasing is used to realize the lowest power 32 KHz crystal oscillator circuit [42]. Sub-threshold operation of CMOS transistors can achieve extremely low power consumption and achieve highest power efficiencies [43, 44]. However, sub-threshold operation has long been associated with high variations of outputs due to process, temperature, or voltage variations. This deficiency of sub-threshold operation can be removed using constant gm analog circuits. In actuality, it is with sub-threshold device operation that one can achieve very precise outputs for various fundamental analog circuits, which is used for PDE solver. To achieve highly stable outputs, we utilize the transconductance gm of a device biased in sub-threshold that is very stable, a concept that was presented in 1970s by the early makers of electronics watch [45]. FIGS. 1A-1H show an example differential amplifier and a low-pass filter implemented with sub-threshold operation achieving high stability of 48 ppm/° C. simulated over a 120° C. temperature range.

Concept Behind Precision Analog Circuits

The transconductance, g_(m), of a transistor biased in sub-threshold is given by

$\begin{matrix} {g_{m} = \frac{I_{O}}{\eta \; V_{t}}} & (1) \end{matrix}$

where I_(O) is the bias current, η is a process constant V_(t) is the thermal voltage. Further, a proportional-to-absolute temperature (PTAT) current reference can be used to bias the transistor, realizing a constant g_(m) circuit. FIG. 1A shows a conventional PTAT current reference circuit where IO is given by,

$\begin{matrix} {I_{O} = \frac{V_{t}\ln \; M}{R_{1}}} & (2) \end{matrix}$

We use equations 1 and 2 to realize the differential amplifier (diff-amp) shown with a g_(m) obtained through PTAT bias and a resistive load R₂. The gain of this diff-amp can be expressed as

$\begin{matrix} {A = {{g_{m}R_{2}} = {\frac{\ln \; M}{\eta}\frac{R_{2}}{R_{1}}}}} & (3) \end{matrix}$

The gain of the diff-amp in equation 3 is a constant, where the only process-dependent parameters are the values of resistors R₁ and R₂, but these are in a ratio that is reliable even with variations. However, for ULP operation both R₁ and R₂ have to be of very large value (over several mega-ohms), which can require very large area. In order to address this aspect, we can make use of switched-capacitor realizations of resistors (SCR), which is illustrated in FIG. 1A. The PTAT current source can be realized by replacing the resistor R₁ through an (SCR), and the gain of differential amplifier in this case is given by,

$\begin{matrix} {A = {\frac{\ln \; M}{\eta}\frac{C_{1}}{C_{2}}}} & (4) \end{matrix}$

Our preliminary analysis shows that the differential amplifier achieves a temperature stability of 48 ppm/° C. It exhibits a 3-σ process variation of 2.3%. The gain of the differential amplifier achieved through this structure is very precise and does not vary with temperature and process. This work was recently published at International Symposium on Circuits and Systems (ISCAS) [46]. These circuits along with the underlying concept can be used to develop bigger analog macros such as multipliers, adders, and pooling-networks, to implement the analog computing system for vision.

Vision ASIC Architecture

The ImageNet challenge is a comprehensive image classification task that has led to several award winning CNN architectures [8-18]. However with each new architecture, the network has only grown deeper which needs more compute resources and power. AlexNet, for example, takes 6 days and GoogleNet takes 21 days to train on NVIDIA-K80 GPU [47] and involve several TFLOPs of computation. Certainly, these networks cannot be used for self-powered vision applications. In fact, it is difficult to realize a much simpler CNN network such as LeNet-5 [48] for character recognition in such power budgets using existing digital hardware. However, analog computing hardware can provide higher energy and area efficiency and should be able to implement simpler CNN at the edge. In this project, we propose to implement a modified LeNet-5 CNN for vision applications. We will use a lower complexity CIFAR-10 datasets which has 60K 32×32 images that can be put in 10 different classes. CIFAR-10 has also been used by other vision projects for IoT edge devices [37,49]. A CNN that can classify CIFAR-10 can be potentially used in applications where smaller classification set can exists such as remote-surveillance, navigation (particularly in industrial set-up), applications involving drones, among others.

FIG. 2 shows the CNN architecture used for CIFAR-10 classification. This CNN architecture is a modified version of LeNet-5 commonly used for gray-scale character recognition [48]. The first stage will have 5×5 (×3) convolution stages. The convolution is carried out in analog with image pixel being represented as voltages and weights represented as currents. The output of the convolution is passed through a Rectified Linear Unit (ReLU) layer which will work as an activation function. This step is an addition over classical LeNet-5 architecture and takes advantage of ReLU nonlinearity for faster learning. An analog realization of ReLU, called A-ReLU will also be developed. Compared to a digital implementation of ReLU which is given as ƒ(x)=max(0,x), A-ReLU is given by ƒ(x)=max(V_(ACT), x), where V_(ACT) is a trainable activation voltage at each layer. There is a clear advantage having a programmable activation voltage at each layer. The training of V_(ACT) will provide a coarser threshold for neuron activation and weights in the filter can provide finer training. In digital implementation of ReLU, only weights can train and ReLU threshold is set to 0. The proposed A-ReLU implementation is more akin to a biological neuron firing.

The convolution layer and A-ReLU layer is followed by a Max-Pooling layer which is also be implemented in analog. These stages are followed by another convolution, A-ReLU, Max-Pooling layer. The output from final Max-Pooling layer is used in two ways. Inside the ASIC, it is connected to fully connected (FC) layer of 10 outputs to reduce the memory foot-print. The output of final Max-pooling layer is connected to two FC layers as shown in FIG. 2. In the following sections, we will provide the details of proposed analog-ASIC shown in FIG. 2. The hardware implementation is more general that can accommodate other simpler CNN architectures as well.

Image Acquisition and Quality

The proposed analog-ASIC diverges from a digital design right from the first step of image acquisition, which sets the fundamental limit on the accuracy of all computations that follows. Despite this difference, we aim to maintain similar or better accuracy than digital by acquiring the image at a better SNR than 8-bit digital. Proposed image acquisition doesn't use ADC to convert the pixel voltage into a digital output. We carry out image acquisition in a manner which is more suitable for analog processing.

FIG. 3A shows the circuit architecture of a 3-T pixel interfaced with an analog multiplier that follows a design proposed in [50]. A DC offset current, I_(OFF) is subtracted from the photo-current (IPIX) to retain the interesting AC component. This structure can provide up to 150 dB dynamic range [50]. FIG. 3A shows the image acquisition which is similar to correlated double sampling (CDS) technique [51] that has better noise performance. When the pixel is reset, its output is set to V_(REF). After reset is released, the pixel voltage is sampled for a set time t_(S). The sampled voltage on the capacitor C_(j) is given

${{\Delta \; V} = {{V_{PIX} - V_{REF}} = \frac{\left( {I_{OFF} - I_{PIX}} \right)t_{s}}{C_{j}}}},$

where I_(PIX) is the current from the photo diode and I_(OFF) is used to remove the DC component in the image. The sampling time, t_(S) can be chosen to be large to realize a large dynamic range output voltage. However, this approach is good for ADC but is not suited for analog computing as it will immediately lead to saturation and non-linearities in the succeeding computing blocks. We will set the value of C₁ to approximately 2 pF. The equivalent RMS noise of this capacitor is approximately 32 μV. We will choose a shorter sampling time, t_(S) to keep the maximum value of ΔV around 10-20 mV. This will prevent non-linearities in next blocks. Further, shorter sampling time also helps in reducing the power consumption.

If the maximum voltage of ΔV is 10 mV on a 2 pF cap, then the SNR of the input signal (pixel voltage) is given by 10 mV/32 μV, which is approximately 50 dB. An 8-bit ADC that is limited by quantization noise also has an SNR of 50 dB. Proposed image acquisition circuit acquires similar or better quality images when compared to an 8-bit digital acquisition (commonly used resolution) at lower power and at a faster rate. To illustrate this point, a 100 nA pixel current will take 0.2 μs to charge a 2 pF C₁ to 10 mV. But we can sample 100 pixel in parallel for computing (explained later), realizing an effective sampling rate of 0.5 GS/s. A similar sampling rate in digital-processing will require an ADC conversion step consuming 10-100s of mW power for an effective 8-bit conversion [52, 53]. That step, and hence the associated power is completely eliminated in the proposed analog computing platform.

Some of the recent works published at ISSCC makes a case for using 6-bit and 4-bit ADC for vision applications [54, 55]. However, one of the cornerstone of the proposed design is high precision and it is believed that high precision analog computing will also enable various other alternate technologies such as on-chip PDE solvers, reducing the need for process and temperature calibration to reduce test times, among others. In this project, even higher SNR can be realized and then can be traded off with power consumption.

Multiplication Circuit

FIG. 2A shows a high precision sub-threshold diff-amp circuit for realizing the analog multiplier. FIG. 4A shows the circuit architecture of an analog multiplier using a diff-amp biased in sub-threshold with a bias current I_(Wi). The input signal, ΔV is directly obtained from the pixel, while the current I_(Wi) is a weight in the convolution filter. The output voltage V_(Oi) is given by,

$\begin{matrix} {V_{Oi} = {{\Delta \; V*g_{m}*R} = {\frac{I_{Wi}}{\eta \; V_{t}}*\Delta \; V*R}}} & (5) \end{matrix}$

The output voltage, V_(Oi) given by equation 5 is a product of pixel voltage and weight for small values of ΔV. We intentionally choose 10 mV of maximum output voltage for the pixcel as diff-amp will quickly become non-linear. FIG. 4B shows the simulation results of the analog multiplier circuit and its comparison with an ideal multiplication in 130 nm CMOS. FIG. 4B shows an almost complete match with a maximum error of ±2% for entire output range. Power Performance Knob: The resistor in the diff-amp is implemented as an SCR, and weights are binary weight of the primary PTAT current. We can maintain the same gain for the diff-amp by increasing switching frequency of the SCR. It increases the value of I_(Wi) and reduces the resistor value by same amount maintaining the same gain. This is used by EMS to scale system performance with power consumption.

The multiplier circuit shown in FIG. 4A is very simple and is implemented using very few transistors. The weight current, I_(Wi) can be implemented as a 4-bit binary weight of the PTAT current reference shown in 2A. The PTV variation of the multiplier can be made very small as detailed below. The training weights for each I_(Wi) is 5-bit, 4-bit binary weights of the PTAT current and one sign bit, which is used in the multiply and accumulate (MAC) circuit discussed below. Weights can be stored in the SRAM. Note that the multiplier is quite compatible with an analog multiplier where weights can be directly entered as analog current, I_(Wi) from the analog memory. However, a complete analog implementation of a CNN, such as in [38] has to address the PTV variation of analog memory or of the associated read-out circuit [56]. Although, CNNs can work with limited accuracy [57], it is still important for practical implementation of a CNN to have very low PTV variation as variations tend to be rather large if not controlled. We will use our precision analog computing platform to have very little PTV variation which has been detailed above.

Multiply and Accumulate (MAC) Unit

FIG. 5A shows the analog circuit approach used for a MAC unit. The output of each analog multiplication as shown in FIG. 4A is sampled across the capacitor C_(Mi). We configure the circuit for MAC to operate in two phases. In phase φ₁, all the associated multiplication happens and voltages are sampled across the capacitors. In phase φ₂, the capacitors are connected in series. The output voltage in phase φ₂ is given by,

$\begin{matrix} {V_{OUT} = {{\Sigma \; V_{Oi}} = {{k*{\Sigma \left( {\Delta \; V_{i}*I_{Wi}} \right)}} = {\frac{\ln \; M}{\eta}\frac{C_{1}}{C_{2}}{\Sigma \left( {\Delta \; V_{i}*W_{i}} \right)}}}}} & (6) \end{matrix}$

V_(OUT) given by equation 6 is sampled on an output capacitor using switching capacitor technique similar to one outlined in an ISSCC paper [58]. V_(OUT) will also have very low PTV variation as the term outside of the summation in equation 6 is a physical constant. Further, the weights can also be negative and is addressed by using a fifth sign bit for the weight. The sign bit will add the capacitor with an inverse configuration. FIG. 5A illustrates this concept. If a sign bit is 0, indicating a negative weight, φ_(2si) switch is enabled instead of φ₂ inversing the polarity of that multiplicand when added in the switched capacitor network.

The maximum gain of the diff-amp in the multiplier is set to 5, meaning gain is 5 when I_(Wi) is maximum. The maximum value of V_(Oi) is equal to 50 mV as shown in FIG. 4B to prevent saturation. In the first stage convolution, 25 MAC operation is carried out for each depth (RGB) of the image. The typical maximum voltage for V_(OUT) will go to ±0.625V, which can be easily handled in a system with a power supply of 1.3V. Further, diff-amp circuits can be prone to mismatch. This effect is mitigated in two ways. First, we use standard analog layout technique such as common-centroid layout of diff-pair to eliminate a significant component of systematic offset. We also employ chopping technique to remove the offset and low-frequency noise from the circuit in a two phase manner similar to [51]. Two-phase chopping (not shown here) will first sample the offset at the output of each amplifier's capacitor while connecting each input to V_(REF) and then subtracting it from the final MAC output.

Alternative Multiplication Circuit and MAC Unit

FIG. 8A shows the circuit architecture of an alternative analog multiplier embodiment using a differential amplifier biased in sub-threshold with a bias current I_(Wi), and a switching capacitor load. The input signal, ΔV, can be directly obtained from a pixcell, while the current I_(Wi) is the value of the weight in an ML application. The load capacitors are reset to 0 every time a MvM operation is started and the differential amplifier is operated for a fixed time of T_(ON) (provided by a system clock). The output voltage V_(Oi), that is generated by the differential amplifier, and is given by:

$\begin{matrix} {V_{Oi} = {{\Delta \; {V \cdot g_{m} \cdot \frac{T_{ON}}{C}}} = {{\frac{I_{Wi}}{\eta \; V_{t}} \cdot \Delta}\; {V \cdot \frac{T_{ON}}{C}}}}} & (7) \\ {V_{Oi} = {{K \cdot W_{i} \cdot \Delta}\; V}} & (8) \end{matrix}$

I_(Wi) can be generated as a binary weight of the PTAT reference current, which makes K a product of physical constants. The output voltage, V_(Oi), given by equation 8, is the product of the pixcell voltage and the weights for small values of ΔV. This circuit performs linearly for an input voltage ΔV of up to 40 mV. There is some compression for the value of gm, as value of the bias current increases, which we address by adding a compensating current with each binary weight of the current. FIG. 8B shows simulation results of our early design space exploration and compares it with an ideal output of the multiplication. Overall, we achieve a highly linear behavior, with an error of less than 1% in the output value of the multiplication, with ΔV varying from 0-40 mV and a current weight variation of 7-bits for the magnitude and 1-bit for the sign. These values are used in the addition circuit (discussed in below), giving us an 8-bit resolution. Furthermore, the input signal can be adequately represented in 40 mV, with a sufficient noise margin for an 8-bit multiplication. Note that it is not unusual to represent analog signals at lower voltage swings, since it saves power. Our approach is similar to the behavior of neurons, where a signal is represented at 50-100 mV swings. Details on how a 40 mV signal will have an adequate noise margin is discussed below.

Addition/Reduction

Once the multiplication has been performed, we need to add outputs to arrive at the MvM result. FIG. 9A shows the circuit approach used for addition. The output of each analog multiplication, as shown in FIG. 8A, is sampled across the differential capacitors C. We configure the circuit for MvM to operate in two phases. In phase φ₁, all the associated multiplications are computed and voltages are sampled across the capacitors. In phase φ₃, the capacitors are connected in parallel to the add. The output voltage in phase φ₃ is given by,

$\begin{matrix} {V_{NEXT} = {{{\frac{1}{n} \cdot \Sigma}\; V_{Oi}} = {{\frac{1}{n} \cdot {\Sigma \left( {\Delta \; V_{i}*I_{Wi}} \right)}} = {\frac{\ln \; M}{n \cdot \eta}{\Sigma \left( {\Delta \; V_{i}*W_{i}} \right)}}}}} & (9) \end{matrix}$

The output voltage V_(NEXT), given by equation 9, is ready to be used by the next layer for multiplication, as shown in FIG. 9B. Additionally, the sign bit (i.e., the eighth bit of the weight) is used to choose the polarity of the addition. In case of a negative output, we can reverse the output capacitors of the multiplier to be added to the network to result in a subtraction of charge.

A-ReLU and Max-Pooling Circuit

The output voltage, V_(OUT) after being sampled is passed through the A-ReLU block. The A-ReLU circuit is simple to realize and is shown in FIG. 6A. V_(OUT) is compared with a trainable activation voltage V_(ACT), using a comparator. The output of the comparator is used to select between V_(OUT) and V_(ACT) which can be sent to the Max-Pooling layer. It realizes the rectifier function ƒ(x)=max(V_(ACT), x). The proposed design provides an ability to train V_(ACT) as well, which provides additional training point while conventional ReLU has a fixed threshold of 0. The Max-Pooling circuit is shown in FIG. 6B uses three A-ReLU units. Two pairs of inputs are compared using two A-ReLU units to give the maximum of each pairs. The outputs are then fed to the third layer to give the maximum of the four inputs.

Second-Stage Multiplier and Scaling

The Max-Pooling is again followed by a convolution layer in the proposed CNN. At this stage, we again need to perform MAC operations. The output voltage coming out of Max-Pooling layer is going be a large signal due to the MAC operation which needs to be scaled down to be used with diff-amp multiplier. FIG. 7 shows the voltage scaling circuit using capacitive charge sharing. The pooling voltage that comes out of the Max-Pooling layer is either be equal to or larger than V_(ACT). This differential voltage is first stored on a capacitor of a value of 20 ƒF in phase φ₁. In phase φ₂, this capacitor gets connected in parallel to a 2 pF capacitor having no charge. The resultant capacitor voltage is approximately 100× lower. This voltage can be then fed to the diff-amp multiplier.

The output of the final Max-Pooling layer is handled in two different ways. Inside the ASIC, it gets connected to an FC of 10 outputs. This is done to reduce the memory foot-print needed on-chip. Note that most of the systems store their FCs in DRAM and energy involved in accessing those is significantly large [59]. Each connection inside the FC implemented on the chip will require 400 MAC operation. This operation is carried out in 4 steps, each step performing the first 100 operation. A total of 4000 MAC operations are carried out in this step.

Exemplary ASIC Implementation

The ASIC design considers power, area, physical design, and control flow of the chip. Some of the design aspects are discussed below:

-   -   We use 100 differential amplifier in the ASIC which will support         4 parallel MAC operations, as each filter in the convolution         layer is 5×5. A total of 210 pF for the MAC network including         100 diff-amps.     -   Each image pixel has 2 pF output capacitor to meet the noise         margin. A total of approximately 150 pF capacitance is needed         for sampling 75 image pixel voltages to the Multiplier. Also,         capacitive memory holds the value of intermediate matrices. A         total 3-4 nF capacitance is needed for the chip.     -   The design heavily uses capacitors and a total of about 4 nF         capacitance are used for the design. An n-MOS capacitor of         approximately 10 μm×10 μm gives a capacitance of 1 pF. Scaling         that calculation up and placing design margins a 1 mm×1 mm area         will sufficiently meet the total capacitance requirement. We use         n-MOS caps for decoupling and storing analog voltages, and MIM         caps at sensitive computing units such as load resistors and         MAC.     -   A 64 KB on-chip SRAM is used for storing the weights. The size         of the ASIC lies between 3 mm×3 mm to 4 mm×4 mm to include all         the components of the chip.     -   Analog multiplication is highest power and will require most         bandwidth and takes about 100 μs to at 40 nA average bias. A 100         multiply and 100 addition will take 100 μs. Assuming an average         of 40 nA for all multipliers in action, we will have 400 nW for         200 operations resulting in an overall power efficiency of 20         TOPs/W. We estimate that the total power consumption for the         chip is less than 2 μW which can be supported through energy         harvesting. At this rate ASIC can process 2 frames per-second         (fps).

ASIC Architecture and Control

FIG. 9 shows a conceptual architecture of the vision ASIC. The energy monitoring system acts as the primary controller and controls how images are sampled and processed. Vision ASIC includes pixel array, capacitor arrays for analog memory, energy harvesting and power management unit (EHM), 64 KB SRAM, EMS, analog multiplier and computing block, and a real-time clock. The ASIC can be primarily developed for CFAR-10 but can be used in vision application where smaller and targeted classification-set of images exist, such as surveillance. The training and the learning of the ASIC is carried out in a closed set-up inside the lab to learn the weights. In the field application space, vision ASIC can be controlled to operate in the following modes with the estimated power consumption:

-   -   Motion Detection Mode: In a motion detection mode, the ASIC         compares the current image with the background. It only uses the         analog multiplier and MAC unit. The analog multiplier uses a         fixed current of 40 nA and performs a 5×5 convolution with a         stride of 5 on a 30×30 gray-scale image input. This results in         36 MAC outputs that are compared with previously calculated         values. If a change is seen in more than two outputs, it is         likely to indicate a motion. Motion detection can be performed         every 0.5 s. A total of 900 MAC operations can be used to run it         once, which will need 1 ms and consume 1.2 μW for 1 ms. The         average power consumption is 3 nW in this case.     -   Object Detection Mode: Once a motion is detected, the ASIC will         start capturing images to extract relevant feature for object         recognition or vision. It will operate in the LeNet-5 mode,         which is discussed in the previous section, where all weights         will be used across each layer. The estimated power consumption         in this mode is less than 2 μW while processing at 2-fps.     -   Video Application: At higher power levels, the ASIC can also         target video applications by going in higher performance mode.         By increasing the switching frequency of switched-cap network by         8×, bias currents are increased by 8× but ASIC functionality         stays the same as multiplier gain is not changed. However, this         will increase the performance by 8×, with ASIC processing at         15-fps, reaching the video processing capability.

Energy Monitoring Control Mechanism

In a typical operating mode, the vision ASIC can operate at 2-fps and perform vision tasks after a motion has been detected. This is also an intermediate power consumption mode. If the energy monitoring system identifies that this operating mode cannot meet the predicted lifetime, then it starts scaling down the frame rate and will go down to 0.1-fps. It can also reconfigure stride and filter size used in convolution. A lightweight network with fewer filters and reduced accuracy can also be trained. An increase in stride to 2 in the first convolution filter, use of gray-scale image, and a reduction in the number of filters to 3 in the first stage alone can reduce the power consumption by 12×. For higher performance mode, the switching frequency of switched capacitor network can be increased to realize higher fps.

Having thus described several illustrative embodiments, it is to be appreciated that various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to form a part of this disclosure, and are intended to be within the spirit and scope of this disclosure. While some examples presented herein involve specific combinations of functions or structural elements, it should be understood that those functions and elements may be combined in other ways according to the present disclosure to accomplish the same or different objectives. In particular, acts, elements, and features discussed in connection with one embodiment are not intended to be excluded from similar or other roles in other embodiments. Additionally, elements and components described herein may be further divided into additional components or joined together to form fewer components for performing the same functions.

Accordingly, the foregoing description and attached drawings are by way of example only, and are not intended to be limiting.

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1. An analog computing method, comprising: (a) generating a biasing current (I_(Wi)) using a constant gm bias circuit operating in the subthreshold region for ultra-low power consumption, wherein gm is generated by PMOS or NMOS transistors, said circuit including a switched capacitor resistor; and (b) multiplying the biasing current by an input voltage using a differential amplifier multiplication circuit to generate an analog voltage output (V_(Oi)).
 2. The method of claim 1, wherein method is used in a vision application, and wherein the biasing current represents a weight in a convolution filter, and the input voltage represents a pixel voltage of an acquired image.
 3. The method of claim 2, wherein the vision application comprises image classification using a convolutional neural network (CNN).
 4. The method of claim 1, wherein the differential amplifier multiplication circuit comprises a pair of transistors coupled at their sources for receiving the biasing current, wherein the input voltage is applied to the gates of the transistors, and wherein the drains of the transistors are coupled to a capacitor across which the analog voltage output of the amplifier multiplication circuit is sampled.
 5. The method of claim 1, wherein the differential amplifier multiplication circuit comprises a pair of transistors coupled at their sources for receiving the biasing current, wherein the input voltage is applied to the gates of the transistors, and wherein the drains of the transistors are each coupled to a load capacitor, and wherein the analog voltage output of the amplifier multiplication circuit is sampled across the drains.
 6. The method of claim 1, further comprising, in a second phase, adding the analog voltage output to an analog voltage output of each of a plurality of additional analog differential amplifier multiplication circuits in a multiply and accumulate unit to generate a voltage output for the multiply and accumulate unit.
 7. The method of claim 6, further comprising comparing the voltage output of the multiply and accumulate unit with a trainable activation voltage using a comparator.
 8. The method of claim 7, wherein the steps of the method are implemented in an application-specific integrated circuit (ASIC).
 9. An analog computing circuit, comprising: a constant gm bias circuit operating in the subthreshold region for ultra-low power consumption for generating a biasing current (I_(Wi)), wherein gm in the constant gm bias circuit is generated by PMOS or NMOS transistors, said constant gm bias circuit including a switched capacitor resistor; and a differential amplifier multiplication circuit coupled to the constant gm bias circuit for receiving the biasing current and an input voltage and multiplying the biasing current by the input voltage to generate an analog voltage output (V_(Oi)).
 10. The analog computing circuit of claim 9, wherein the analog computing circuit is used in a vision application, and wherein the biasing current represents a weight in a convolution filter, and the input voltage represents a pixel voltage of an acquired image.
 11. The analog computing circuit of claim 10, wherein the vision application comprises image classification using a convolutional neural network (CNN).
 12. The analog computing circuit of claim 9, wherein the differential amplifier multiplication circuit comprises a pair of transistors coupled at their sources for receiving the biasing current, wherein the input voltage is applied to the gates of the transistors, and wherein the drains of the transistors are coupled to a capacitor across which the analog voltage output of the amplifier multiplication circuit is sampled.
 13. The analog computing circuit of claim 9, wherein the differential amplifier multiplication circuit comprises a pair of transistors coupled at their sources for receiving the biasing current, wherein the input voltage is applied to the gates of the transistors, and wherein the drains of the transistors are each coupled to a load capacitor, and wherein the analog voltage output of the amplifier multiplication circuit is sampled across the drains.
 14. The analog computing circuit of claim 9, further comprising a multiply and accumulate unit for adding the analog voltage output to an analog voltage output of each of a plurality of additional analog differential amplifier multiplication circuits in a second phase to generate a voltage output for the multiply and accumulate unit.
 15. The analog computing circuit of claim 14, further comprising a comparator for comparing the voltage output of the multiply and accumulate unit with a trainable activation voltage.
 16. The analog computing circuit of claim 15, wherein the analog computing circuit is implemented in an application-specific integrated circuit (ASIC). 